Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. Here i will show you a simple circuit which is use to detect Positive as well negative edges.
VHDL CODE :
library ieee;
use ieee.std_logic_1164.all;
entity edge is
port (
inp : in std_logic; -- inpit
clk : in std_logic; -- clock
rst : in std_logic; -- reset
edge_op : out std_logic); -- setected edge output
end edge;
architecture edge_ar of edge is
signal sig1 : std_logic; -- signal from 1st flop
signal sig2 : std_logic; -- signal from 2nd flop
begin -- edge_ar
edge : process(clk, rst)
begin
if rst = '1' then
sig1 <= '0';
sig2 <= '0';
elsif clk'event and clk = '1' then
sig1 <= inp;
sig2 <= sig1;
end if;
end process edge;
edge_op <= sig1 xor sig2;
end edge_ar;
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