HDL Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

Netgen - The Circuit Netlist Comparison (LVS) and Netlist Conversion Tool

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).

Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.

DOWNLOAD

IRSIM - tThe Switch-level Digital Circuit Simulator.

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

IRSIM shares a history with magic, although it is an independent program. Magic was designed to produce, and IRSIM to read, the ".sim" file format, which is largely unused outside of these two programs. IRSIM was developed at Stanford, while Magic was developed at Berkeley. Parts of Magic were developed especially for use with IRSIM, allowing IRSIM to run a simulation in the "background" (i.e., a forked process communicating through a pipe), while displaying information about the values of signals directly on the VLSI layout.

For "quick" simulations of digital circuits, IRSIM is still quite useful for confirming basic operation of digital circuit layouts. The addition of scheduling commands ("at", "every", "when", and "whenever") put IRSIM into the same class as Verilog simulators. It is, in my opinion, much easier to write complicated testbench simulations using Tcl and IRSIM. I have used IRSIM to validate the digital parts of several production chips at MultiGiG, including the simulation of analog behavior such as PLL locking.

IRSIM version 9.5 was a long-standing and stable version that corresponded to the relatively stable Magic version 6.5. When magic was recast in a Tcl/Tk interpreter framework (versions 7.2 and 7.3), IRSIM could no longer operate as a background process. However, it was clear that if IRSIM could also be recast in the same Tcl/Tk interpreter framework, the level of interaction between it and Magic would be greatly increased.

I set about to create the "new" IRSIM, although it came along in fits and starts as I had time to work on it. Because the original "analyzer" graphic display window (and GUI, to a very limited extent) was written in Xt (the rather primitive window system that is an integral part of X11), it was scrapped for a while. In its place, I substituted graphs in "Blt" based on the same in "tclspice" (see SourceForge for the tclspice project). Unfortunately, "Blt" insists that all data vectors must be real-valued, which is 1) a severe waste of space for binary digital values, and 2) is unable to represent the concept of an "unknown" value that is so crucial to fast switch simulation. So, eventually I was forced to scrap BLT and actually sit down and code out a real Tcl-based analyzer window and GUI. The result is finally done in revision 9.7.3.

DOWNLOAD

XCircuit - The Circuit Drawing and Schematic Capture Tool

There are drawing programs, and there are schematic capture programs. All schematic capture programs will produce output for inclusion in publications. However, these programs have different goals, and it shows. Rarely is the output of a schematic capture program really suitable for publication; often it is not even readable, or cannot be scaled. Engineers who really want to have a useful schematic drawing of a circuit usually redraw the circuit in a general drawing program, which can be both tedious and prone to introducing new errors.

XCircuit is a UNIX/X11 (and Windows, if you have an X-Server running, or Windows API, if not) program for drawing publishable-quality electrical circuit schematic diagrams and related figures, and produce circuit netlists through schematic capture. XCircuit regards circuits as inherently hierarchical, and writes both hierarchical PostScript output and hierarchical SPICE netlists. Circuit components are saved in and retrieved from libraries which are fully editable. XCircuit does not separate artistic expression from circuit drawing; it maintains flexiblity in style without compromising the power of schematic capture.

DOWNLOAD

Magic - The VLSI Layout Editor, Extraction, and DRC Tool.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

DOWNLOAD

Xilinx ISE Design suite 10.1

Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design environment that allows you to design Xilinx FPGA and CPLD devices from start to finish. ISE includes our world class design entry, synthesis and implementation tools delivering the industry's fastest place and route times, highest performance, and most advanced design methodologies.

Project Navigator is the user interface that helps you manage the entire design process including design entry, simulation, synthesis, implementation and finally download the configuration of your FPGA or CPLD device.

The following is an outline of the features offered in ISE.

Design Entry

• HDL Editor
• StateCAD State Machine Editor
• Schematic Editor - Engineering Capture System (ECS)
• CORE Generator

Synthesis

• XST - Xilinx Synthesis Technology
• Integration with LeonardoSpectrum from Mentor Graphics, Inc.
• Integration with Synplify from Synplicity, Inc.

Simulation

• HDL Bencher Testbench Generator
• Integration with ModelSim Simulator from Model Technology, Inc.

Implementation

• Translate
• MAP
• Place and Route (PAR)
• Floorplanner
• FPGA Editor
• Timing Analyzer
• XPower
• Fit (CPLD only)
• Chipviewer (CPLD only)

Device Download and Program File Formatting

• BitGen
• iMPACT

Download the Xilinx ISE 10.1 design suit from Here